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International Transactions on Computer Hardware and Electrical Engineering
Vol. 4, No. 2, Jun. 2018
Latest trends in Hardware Verification | Miscellaneous
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a Intel Corporation, San Jose, USA
Mr. Joydeep Bhattacharyya
 Corresponding Author
 Affiliation: Intel Corporation, San Jose, USA
 Tel: +1-908-2025424
 E-mail: joydeep.bhattacharyya@intel.com
2nd e-mail: joydeep.bh@gmail.com  Biography: I have been actively involved in Research and Development of Hardware Design for Medical imaging, image processing and networking applications. At present, I am working as a Senior Chip Design Engineer at Intel Corporation’s Silicon valley, California office. Before that, I have designed several multi-million gate, first-of-its-kind chips for companies such as Ericsson and Juniper Networks. I hold a Master’s degree in Electronics and Communications Engineering from the prestigious Indian Institute of Technology, Kharagpur, India.
Mr. Joydeep Bhattacharyya's publications in ICSES
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This article has been retracted by International Computer Science and Engineering Society (ICSES) because of ethical misconduct, scientific distortion, or administrative error, and cannot be downloaded and used for any purpose based on the violation in ICSES Ethics in Publicationcall_made |
Retraction Note by the Editor-in-Chief
Highlights and Novelties
1. Prioritization strategies on chip verification
2. How coverage driven random stimuli creates hard to reach corner-cases
3. Simulation based vs property based (assertion/formal) techniques
Manuscript Abstract
Chip design complexity has grown in the past two decades at an exponential rate. In this era of multi-million gate System on Chip (SOC) designs, the verification activity consumes more than 70% of the total project effort. The cost of a design bug and subsequent re-spin of the chip is in the order of tens of millions of dollars. However, exhaustively verifying the design for all possible input and state-space conditions is a seemingly impossible task. This paper has tried to capture the state of the art verification methodologies used for present day ASIC and FPGA design. It explains the philosophy behind coverage driven constraint random verification, something that has revolutionized the chip verification industry. The paper also talks about two recently introduced techniques, namely assertion and formal verification. Compared to the traditional simulation based verification methodologies, formal and assertion methods provide a more complete coverage, but at the expense of more compute resource and time.
Keywords
Chip Design Constraint Random Verification Assertion Formal Verification
Copyright and Licence
© Copyright was transferred to International Computer Science and Engineering Society (ICSES) by all the Authors. This manuscript is published in Open-Access manner based on the copyright licence of Creative Commons Attribution Non Commercial 4.0 International (CC BY-NC 4.0).
Cite this manuscript as
Joydeep Bhattacharyya, "Latest trends in Hardware Verification," International Transactions on Computer Hardware and Electrical Engineering, vol. 4, no. 2, pp. 1-2, Jun. 2018.
For External Scientific Databeses
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